1. Field of the Invention
The present invention generally relates to the control of instructions to a pipelined processor of a stored program data processing machine and, more particularly, to a priority selection logic circuit to select the next instruction to be executed in a microprocessor having an architecture where instructions are executed out of sequence to achieve higher performance.
2. Description of the Prior Art
A microprocessor that is capable of issuing and executing machine instructions out of sequence can theoretically achieve a performance improvement of as high as 50%. However, the potential performance gain can be severely limited in actual practice due to the design of the instruction selection logic. Priority selectors are known which use either a tree or a chain structure. A tree structure with twelve inputs needs four levels (log.sub.2 12). In order to resolve, a signal needs to propagate from the lowest level of the tree to the top and back again to the bottom. The signal thus needs to traverse seven nodes to get to the output. In a fixed order priority selector, the logic at each node has to be at least one level deep. In a rotating priority selector, the logic at each node is considerably more complex and needs to be at least two or more levels deep. An optimum design in a twelve bit rotating priority selector in a tree structure would result in a fourteen stage delay path. The logic depth for a chain structure scales linearly by the number of inputs to be resolved. For a fixed priority selector, this would result in a twelve stage delay path. A twelve bit rotating priority selector would add at least one stage to the overall delay path yielding a critical path of thirteen gate delays.